CMOS QUAD 3-STATE R/S LATCHES

文件：211.83 Kbytes 页数：13 Pages

TI

德州仪器

CMOS Quad 3-State R/S Latches

文件：1.66221 Mbytes 页数：31 Pages

TI

德州仪器

CMOS QUAD 3-STATE R/S LATCHES

文件：211.83 Kbytes 页数：13 Pages

TI

德州仪器

CMOS QUAD 3-STATE R/S LATCHES

文件：211.83 Kbytes 页数：13 Pages

TI

德州仪器

CMOS Quad 3-State R/S Latches

文件：1.66221 Mbytes 页数：31 Pages

TI

德州仪器

CMOS Quad 3-State R/S Latches

文件：1.66221 Mbytes 页数：31 Pages

TI

德州仪器

具有三态输出的 CMOS 四路或非 R/S 锁存器

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic \"1\" or high on the ENABLE inp • 3-state outputs with common output ENABLE\n• NOR and NAND configurations\n• Standardized symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n• 2 V at VDD = 10 V\n• Meets all requirements of JEDEC Tentative Standa;

TI

德州仪器

CD4043BC Quad 3-STATE NOR R/S Latches • CD4044BC Quad 3-STATE NAND R/S Latches

CD4043BC Quad 3-STATE NOR R/S Latches\nCD4044BC Quad 3-STATE NAND R/S LatchesGeneral Description\nThe CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3-STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The ■Wide supply voltage range: 3V to 15V\n■Low power: 100 nW (typ.)\n■High noise immunity: 0.45 VDD(typ.)\n■Separate SET and RESET inputs for each latch\n■NOR and NAND configuration\n■3-STATE output with common output enableApplications\n• Multiple bus storage\n• Strobed register\n• Four bits of indepe;

ONSEMI

安森美半导体

具有三态输出的 CMOS 四路或非 R/S 锁存器

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic \"1\" or high on the ENABLE inp • 3-state outputs with common output ENABLE\n• NOR and NAND configurations\n• Standardized symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n• 2 V at VDD = 10 V\n• Meets all requirements of JEDEC Tentative Standa;

TI

德州仪器

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC NOR R/S LATCH 3ST QUAD 16SOIC

TI

德州仪器