CMOS Quad 3-State R/S Latches High-Voltage Types (20-Volt Rating) Quad NOR R/S Latch — CD40438 ‘Quad NAND R/S Latch — CD40448

Features: 3-state outputs with common output ENABLE Separate SET and RESET inputs for each latch NOR and NAND configurations 5.V, 10-V, and 15-V parametric ratings = Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V Maximum input current

文件：2.16762 Mbytes 页数：36 Pages

TI

德州仪器

CMOS Quad 3-State R/S Latches

文件：1.66221 Mbytes 页数：31 Pages

TI

德州仪器

具有三态输出的 CMOS 四路或非 R/S 锁存器

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic \"1\" or high on the ENABLE inp • 3-state outputs with common output ENABLE\n• NOR and NAND configurations\n• Standardized symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n• 2 V at VDD = 10 V\n• Meets all requirements of JEDEC Tentative Standa;

TI

德州仪器

CMOS Quad Clocked ?쏡??Latch

Description CD4043BMS types are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or hig

文件：110.1 Kbytes 页数：10 Pages

INTERSIL

CMOS Quad 3 State R/S Latches

Features • High Voltage Types (20V Rating) • Quad NOR R/S Latch- CD4043BMS • Quad NAND R/S Latch - CD4044BMS • 3 State Outputs with Common Output ENABLE • Separate SET and RESET Inputs for Each Latch • NOR and NAND Configuration • 5V, 10V and 15V Parametric Ratings • Standardized Symmetric

文件：395.92 Kbytes 页数：10 Pages

RENESAS

瑞萨

CMOS Quad Clocked ?쏡??Latch

Description CD4043BMS types are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or hig

文件：110.1 Kbytes 页数：10 Pages

INTERSIL