CMOS QUAD EXCLUSIVE-OR GATE

文件：497.8 Kbytes 页数：11 Pages

TI

德州仪器

CMOS Quad Exclusive - OR Gate

文件：1.14175 Mbytes 页数：16 Pages

TI

德州仪器

CMOS Quad Exclusive - OR Gate

文件：1.14175 Mbytes 页数：16 Pages

TI

德州仪器

CMOS QUAD EXCLUSIVE-OR GATE

文件：497.8 Kbytes 页数：11 Pages

TI

德州仪器

CMOS QUAD EXCLUSIVE-OR GATE

文件：497.8 Kbytes 页数：11 Pages

TI

德州仪器

4 通道、4 输入、3V 至 18V XOR（异或）门

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.\n\n The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-lineplastic p • Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF\n• Standardized, symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Stan;

TI

德州仪器

军用 4 通道、4 输入、3V 至 18V XOR（异或）门

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.\n\n The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-lineplastic p • Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF\n• Standardized, symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Stan;

TI

德州仪器

CMOS Quad Exclusive-OR Gate

The CD4030BMS types consist of four independent Exclusive- OR gates. The CD4030BMS provides the system designer with a means for direct implementation of the Exclusive-OR function.\nThe CD4030BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H3W • High Voltage Type (20V Rating) \n• Medium-Speed Operation \n• tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF \n• 100% Tested for Quiescent Current at 20V \n• Standardized Symmetrical Output Characteristics \n• 5V, 10V and 15V Parametric Ratings \n• Maximum Input Current Of 1µA at 18V Over Ful;

Renesas

瑞萨

Package：14-DIP（0.300"，7.62mm）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 4CH 2-INP 14DIP

TI

德州仪器

Package：14-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 4CH 2-INP 14SOIC

TI

德州仪器