丝印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器