CD4027BMS中文资料CMOS Dual J-K Master-Slave Flip-Flop数据手册Renesas规格书

描述 Description

CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D type flip-flop.
The CD4027BMS is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip- flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline packages:
Ceramic Flatpack H6W

特性 Features

• High Voltage Type (20V Rating)
• Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either \"High\" or \"Low\"
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range;
• Noise Margin (Over Full Package Temperature Range):
• 2V at VDD = 10V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"

应用 Application

• Registers, Counters, Control Circuits