CD4027BMS

CMOS Dual J-K Master-Slave Flip-Flop

Description CD4027BMSisasinglemonolithicchipintegratedcircuitcontainingtwoidenticalcomplementary-symmetryJ-Kmasterslaveflip-flops.Eachflip-flophasprovisionsforindividualJ,K,SetReset,andClockinputsignals.BufferedQandQsignalsareprovidedasoutputs.Thisinput-out

CD4027BMS

CMOS Dual J-KMaster-Slave Flip-Flop

Features •HighVoltageType(20VRating) •Set-ResetCapability •StaticFlip-FlopOperation-RetainsStateIndefinitely withClockLevelEither“High”or“Low” •MediumSpeedOperation-16MHz(typ.)ClockToggle Rateat10V •StandardizedSymmetricalOutputCharacteristics •100Test

CD4027BMS

CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement ; • High Voltage Type (20V Rating) \n• Set - Reset Capability \n• Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either \"High\" or \"Low\" \n• Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V \n• Standardized Symmetrical Output Characteristics \n• 100% Test;

CD4027BMT

CMOSDUALJ-KMASTER-SLAVERFLIP-FLOP

CD4027BMT

CMOSDualJ-KMaster-SlaveFlip-Flop

CD4027BMT

CMOSDualJ-KMaster-SlaveFlip-Flop