CD4021B-Q1中文资料汽车类 CMOS 8 级静态移位寄存器数据手册TI规格书

描述 Description

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel \"JAM\" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, \"Q\" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is \"forced\" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

特性 Features

• Qualified for Automotive Applications
• Fully Static Operation
• 100% Tested for Quiescent Current at 20 V
• Noise Margin (Full Package-Temperature Range):
• 2 V at VDD = 10 V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard No. 13B,\"Standard Specifications for Description of ’B’ Series CMOS Devices\"
• APPLICATIONS
• Parallel-to-Serial Data Conversion
• General-Purpose Register