CD40192B中文资料CMOS 可预置 BCD 加/减计数器（具有重置功能的双时钟）数据手册TI规格书

描述 Description

CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated \"D\" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\\ ENABLE\\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\\ and BORROW\\ outputs for multiple-stage counting schemes are provided.
The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\\ ENABLE\\ control is low.
The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.
The CARRY\\ and BORROW\\ signals are high with the counter is counting up or down. The CARRY\\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\\ and CARRY\\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.
The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Individual clock lines for counting up or counting down
• Asynchronous reset and preset capability
• 5-V, 10-V, and 15-V parametric ratings
• 100% tested for quiescent current at 20 V
• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V
• Applications:
• Multistage ripple counting
• A/D and D/A conversion
• Programmable binary or BCD counting

简介

CD40192B属于集成电路（IC）的计数器除法器。由TI制造生产的CD40192B计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。