CD40194B中文资料CMOS 4 位双向通用移位寄存器数据手册TI规格书

描述 Description

CD40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET\\ input resets all stages and forces all outputs low.
The CD40194B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Medium-speed: fCL = 12 MHz (typ.) @ VDD = 10 V
• Synchronous parallel or serial operation
• Standardized, symmetrical output characteristics
• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"
• Serial/parallel conversions
• General-purpose registers
NOT RECOMMENDED FOR NEW DESIGNS