CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

文件：686.94 Kbytes 页数：16 Pages

TI

德州仪器

CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

文件：688.43 Kbytes 页数：16 Pages

TI

德州仪器

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes 页数：11 Pages

TI

德州仪器

Dual 4-Bit Static Shift Register

General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

文件：56.38 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual 4-Bit Static Shift Register

General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

文件：56.38 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual 4-Bit Static Shift Register

General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

文件：56.38 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Intersil’s Satellite Applications Flow™ (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of r

文件：74.24 Kbytes 页数：3 Pages

INTERSIL

丝印：CD4015BE；Package：PDIP；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

文件：686.94 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4015BE；Package：PDIP；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

文件：688.43 Kbytes 页数：16 Pages

TI

德州仪器

CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

文件：686.94 Kbytes 页数：16 Pages

TI

德州仪器