CD74HC4543E.A

Marking：CD74HC4543E；Package：PDIP；High-Speed CMOS Logic BCD to 7-Segment Latch/Decoder/Driver for LCDs

Features •InputLatchesforBCDCodeStorage •BlankingCapability •PhaseInputforComplementingOutputs •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •WideOperatingTemper

CD74HC670E

Marking：CD74HC670E；Package：PDIP；High-Speed CMOS Logic 4x4 Register File

Features •SimultaneousandIndependentReadandWrite Operations •Expandableto512Wordsofn-Bits •Three-StateOutputs •Organizedas4Wordsx4BitsWide •BufferedInputs •TypicalReadTime=16nsfor’HC670VCC=5V,CL= 15pF,TA=25oC •Fanout(OverTemperatureRange) -Stan

CD74HC670E.A

Marking：CD74HC670E；Package：PDIP；High-Speed CMOS Logic 4x4 Register File

Features •SimultaneousandIndependentReadandWrite Operations •Expandableto512Wordsofn-Bits •Three-StateOutputs •Organizedas4Wordsx4BitsWide •BufferedInputs •TypicalReadTime=16nsfor’HC670VCC=5V,CL= 15pF,TA=25oC •Fanout(OverTemperatureRange) -Stan

CD74HC75E

Marking：CD74HC75E；Package：PDIP；Dual 2-Bit Bistable Transparent Latch

Features •TrueandComplementaryOutputs •BufferedInputsandOutputs •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •WideOperatingTemperatureRange...-55oCto125oC •B

CD74HC75E.A

Marking：CD74HC75E；Package：PDIP；Dual 2-Bit Bistable Transparent Latch

Features •TrueandComplementaryOutputs •BufferedInputsandOutputs •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •WideOperatingTemperatureRange...-55oCto125oC •B

CD74HCT109E

Marking：CD74HCT109E；Package：PDIP；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features •AsynchronousSetandReset •SchmittTriggerClockInputs •TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •Wi

CD74HCT109E.A

Marking：CD74HCT109E；Package：PDIP；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features •AsynchronousSetandReset •SchmittTriggerClockInputs •TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •Wi

CD74HCT112E

Marking：CD74HCT112E；Package：PDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HCT137E

Marking：CD74HCT137E；Package：PDIP；High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features •SelectOneofEightDataOutputs -ActiveLowforCD74HC137andCD74HCT137 -ActiveHighfor’HC237andCD74HCT237 •l/OPortorMemorySelector •TwoEnableInputstoSimplifyCascading •TypicalPropagationDelayof13nsatVCC=5V, 15pF,TA=25oC(CD74HC237) •Fanout(Over

CD74HCT139E

Marking：CD74HCT139E；Package：PDIP；High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

Features •MultifunctionCapability -Binaryto1of4Decodersor1to4Line Demultiplexer •ActiveLowMutuallyExclusiveOutputs •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoad