CD74ACT109E

Marking：CD74ACT109E；Package：PDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT109E.A

Marking：CD74ACT109E；Package：PDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT10E

Marking：CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCRLatchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT10E.A

Marking：CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCRLatchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD74ACT138E

Marking：CD74ACT138E；Package：PDIP；CDx4ACT138 3-Line to 8-Line Decoders/Demultiplexers

1Features •InputsareTTL-voltagecompatible •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethreeenableinputstosimplify cascadingand/ordatareception •

CD74ACT139E

Marking：CD74ACT139E；Package：PDIP；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage BufferedInputs IncorporateTwoEnableInputstoSimplify Cascadingand/orDataReception SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagation

CD74ACT139E.A

Marking：CD74ACT139E；Package：PDIP；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage BufferedInputs IncorporateTwoEnableInputstoSimplify Cascadingand/orDataReception SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagation

CD74ACT161E

Marking：CD74ACT161E；Package：PDIP；4-BIT SYNCHRONOUS BINARY COUNTERS

InputsAreTTL-VoltageCompatible InternalLook-AheadforFastCounting CarryOutputforn-BitCascading SynchronousCounting SynchronouslyProgrammable SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionper MIL-STD-883,Method3015 description/orderingin

CD74ACT161E.A

Marking：CD74ACT161E；Package：PDIP；4-BIT SYNCHRONOUS BINARY COUNTERS

InputsAreTTL-VoltageCompatible InternalLook-AheadforFastCounting CarryOutputforn-BitCascading SynchronousCounting SynchronouslyProgrammable SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionper MIL-STD-883,Method3015 description/orderingin

CD74ACT163E

Marking：CD74ACT163E；Package：PDIP；4-BIT SYNCHRONOUS BINARY COUNTERS

InputsAreTTL-VoltageCompatible InternalLook-AheadforFastCounting CarryOutputforn-BitCascading SynchronousCounting SynchronouslyProgrammable description/orderinginformation The’ACT163devicesare4-bitbinarycounters. Thesesynchronous,presettablecountersfeature aninte