CBTU4411EE数据手册恩XP中文资料规格书

描述 Description

This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 selectinput levels.
Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). Theselection of the DIMM port to be connected to the Host port is controlled by a decoderdriven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects allDIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1select one of four DIMM ports to be connected to their respective host port. Whendisconnected, any DIMM port is terminated to the externally supplied voltage Vbias bymeans of an on-chip pull-down resistor of typically 400 Ω. The ON-state connects theHost port to the DIMM port through a 12 Ω nominal series resistance. The design isintended to have only one DIMM port active at any time.
The CBTU4411 can also be configured to support a differential strobe signal onchannel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOSconfiguration input strobe enable (STREN) is HIGH, channel 10 is pulled up to 3/4 of VDDinternally by a resistive divider when the DIMM port is idle. When the CBTU4411 isdisabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for currentsavings, pulling channel 10 to VDD. When strobe enable (STREN) is LOW, channel 10behaves the same as all other channels.
The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltageshould be provided to input pin VREF at nominally 0.5VDD. This topology providesaccurate control of switching times by reducing dependency on select signal slew rates.S0 and S1 are provided with selectable input termination to 0.5VDD (active when LVCMOSinput TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1inputs are pulled LOW.
The part incorporates a very low crosstalk design. It has a very low skew between outputs(< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimalperformance in DDR2 data bus applications.
Each switch has been optimized for connection to 1- or 2-rank DIMMs.
The low internal RC time constant of the switch allows data transfer to be made withminimal propagation delay.
The CBTU4411 is characterized for operation from 0 °C to +85 °C.

特性 Features

• Enable (EN) and select signals (S0, S1) are SSTL_18 compatible
• Optimized for use in Double Data Rate 2 (DDR2) SDRAM applications
• Suitable to be used with 400 Mbit/s to 800 Mbit/s, 200 MHz to 400 MHz DDR2 data bus
• Switch ON-resistance is designed to eliminate the need for series resistor to DDR2 SDRAM
• 12 Ω ON-resistance
• Controlled enable/disable times support fast bus turnaround
• Pseudo-differential select inputs support accurate and low-skew control of switching times
• Selectable built-in termination resistors on the Sn inputs
• Internal 400 Ω pull-down resistors on xDPn port
• VBIAS input for optimal DIMM-port pull-down when disabled
• Configurable to support differential strobe with pull-up to 3/4 of VDD on channel 10 when idle
• Low differential skew
• Matched rise/fall slew rate
• Low crosstalk data-data/data-DQM
• Simplified 1 : 4 switch position control by 2-bit encoded input
• Single input pin puts all bus switches in OFF (high-impedance) position
• Latch-up protection exceeds 500 mA per JESD78
• ESD protection exceeds 1500 V HBM per JESD22-A114 and 750 V CDM perJESD22-C101