CBTL06DP211EE数据手册恩XP中文资料规格书

描述 Description

CBTL06DP211 is a multi-channel high-speed multiplexer meant for DisplayPort (DP) v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s or 2.7 Gbit/s. It is designed using NXP® proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP211 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice.
CBTL06DP211 consumes very low current in operational mode (less than 1 mA typical) and provides for a shutdown function (ultra low current consumption less than 10 μA) to support power-sensitive or battery-powered applications. It is designed for delivering optimum performance at DP data rates of 1.62 Gbit/s and 2.7 Gbit/s.
A typical application of CBTL06DP211 is on motherboards where one of two GPU display sources needs to be selected to connect to a display sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth pass-gate technology), the CBTL06DP211 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors.
Optionally, the CBTL06DP211 can be used in conjunction with an HDMI/DVI level shifter device (PTN3360A/B or PTN3360D) to allow for DisplayPort as well as HDMI/DVI connectivity.

特性 Features

• 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1a - 1.62 Gbit/s or 2.7 Gbit/s)
• 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort signals
• 1 channel with 4 : 1 multiplexing/switching for AUX differential signals and DDC single-ended clock and data signals
• 1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals
• High-bandwidth analog pass-gate technology
• Very low lane intra-pair skew (5 ps typical)
• Very low inter-pair skew (< 180 ps)
• Switch/multiplexer position select CMOS input
• Shutdown mode CMOS input
• Shutdown mode delivers ultra low power consumption
• DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
• Supports HDMI/DVI incorrect dongle connection
• Single 3.3 V power supply
• Very low operation current of 0.2 mA typical
• Very low shutdown current of < 10 μA
• ESD 8 kV HBM, 1 kV CDM
• ESD 2 kV HBM, 500 V CDM for control pins
• Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package

应用 Application

需要DisplayPort和PCI Express切换/多路复用的主板应用
扩展底座
笔记本电脑
需要将PCI Express或DisplayPort I/O引脚灵活分配至电路板接口的芯片组