ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

文件：127.85 Kbytes 页数：10 Pages

AZM

ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

文件：127.85 Kbytes 页数：10 Pages

AZM

ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

文件：127.85 Kbytes 页数：10 Pages

AZM

SOT-223

DIODES

美台半导体

上传：深圳市鑫远鹏科技有限公司

BGA

DIODES

美台半导体

上传：深圳万励电子科技有限公司三部