AS4LC4M16DG-5S/IT中文资料AUSTIN数据手册PDF规格书

GENERAL DESCRIPTION

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns.

FEATURES

• Single +3.3V ±0.3V power supply.

• Industry-standard x16 pinout, timing, functions, and package.

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• Extended Data-Out (EDO) PAGE MODE access

• 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH distributed across 64ms

• Optional self refresh (S) for low-power data retention

• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020