AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trilli

文件：5.6225 Mbytes 页数：300 Pages

TI

德州仪器

AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trillio

文件：6.85347 Mbytes 页数：326 Pages

TI

德州仪器

丝印：AM69A98ATGGHAALY259；Package：FCBGA；AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trillio

文件：6.59231 Mbytes 页数：312 Pages

TI

德州仪器

丝印：AM69A98ATGGHAALY259；Package：FCBGA；AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trillio

文件：6.85347 Mbytes 页数：326 Pages

TI

德州仪器

AM69Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trilli

文件：5.44323 Mbytes 页数：299 Pages

TI

德州仪器

AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trilli

文件：5.6225 Mbytes 页数：300 Pages

TI

德州仪器

AM69Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trilli

文件：5.44323 Mbytes 页数：299 Pages

TI

德州仪器

适用于 1-12 个摄像头、自主移动机器人、机器视觉、移动 DVR、AI 盒的 32TOPS 视觉 SoC

AM69 可扩展处理器系列采用不断发展的 Jacinto™ 7 架构，面向智能视觉摄像头应用，基于 TI 在视觉处理器市场上十多年所积累的广泛先进市场知识而构建。AM69x 系列专为工厂自动化、楼宇自动化和其他市场中广泛的成本敏感型高性能计算应用而构建。\n\n AM69 以业界卓越的功耗/性能比为传统和深度学习算法提供高性能计算技术，并且系统集成度高，可为高级视觉摄像头应用实现可扩展性和更低的成本。关键内核包括用于常规计算的新款 Arm 和 GPU 处理器、具有标量和矢量内核的下一代 DSP、专用深度学习和传统算法加速器、集成的下一代成像子系统 (ISP)、视频编解码器和隔离式 MCU 岛。 Processor cores: \n• 2MB shared L2 cache per quad-core Cortex®-A72 cluster\n• Up to Four Deep Learning Accelerators: \n• Total of 32 Trillion Operations Per Second (32 TOPS)\n• Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI \n• Dual-core Arm® Cortex®-R5F MCUs a;

TI

德州仪器