AM69A数据手册TI中文资料规格书

描述 Description

AM69 可扩展处理器系列采用不断发展的 Jacinto™ 7 架构，面向智能视觉摄像头应用，基于 TI 在视觉处理器市场上十多年所积累的广泛先进市场知识而构建。AM69x 系列专为工厂自动化、楼宇自动化和其他市场中广泛的成本敏感型高性能计算应用而构建。

AM69 以业界卓越的功耗/性能比为传统和深度学习算法提供高性能计算技术，并且系统集成度高，可为高级视觉摄像头应用实现可扩展性和更低的成本。关键内核包括用于常规计算的新款 Arm 和 GPU 处理器、具有标量和矢量内核的下一代 DSP、专用深度学习和传统算法加速器、集成的下一代成像子系统 (ISP)、视频编解码器和隔离式 MCU 岛。所有这些都由工业级安全硬件加速器提供保护。

通用计算内核和集成概述：Arm® Cortex®-A72 的两个四核集群配置（共 8 个内核）有助于实现多操作系统应用，且对软件管理程序的需求非常低。最多两个双核（共 4 个内核）Arm® Cortex®-R5F 子系统能够管理低级的时序关键型处理任务，使 Arm® Cortex®-A72 内核不受应用的影响。TI 的第 7 代 ISP 以现有出色的 ISP 为基础，能够灵活地处理更广泛的传感器套件，支持更高的位深度，并且具有面向分析应用的特性。集成的诊断和安全功能可支持高达 SIL-2 级别的运行，同时集成的安全功能可保护数据免受现代攻击。CSI2.0 端口支持多传感器输入。

主要高性能内核概述：C7000™ DSP 下一代内核（“C7x”）将 TI 先进的 DSP 和 EVE 内核整合到性能更高的单个内核中，并增加了浮点矢量计算功能，可实现对旧代码的向后兼容性，同时简化软件编程。即使在 105°C 和 125°C 的最坏情况结温下运行，四个“MMA”深度学习加速器也可在业界超低功率范围内实现高达 32 万亿次每秒运算 (TOPS) [每内核 8TOPS] 的性能。专用的视觉硬件加速器可提供视觉预处理，而不会影响系统性能。C7x/MMA 内核仅可用于 AM69 级处理器中的深度学习功能。

特性 Features

Processor cores:
• Up to eight 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
• 2MB shared L2 cache per quad-core Cortex®-A72 cluster
• 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core

• Up to Four Deep Learning Accelerators:
• Each with up to 8 Trillion Operations Per Second (TOPS)
• Total of 32 Trillion Operations Per Second (32 TOPS)

• Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
• 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM

• Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
• 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories

• Up to two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
• 480 MPixel/s ISP
• Support for up to 16-bit input RAW format
• Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
• Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

• GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
• Multimedia:
• Display subsystem supports:
• Up to 4 displays
• Up to two DSI 4L TX (up to 2.5K)
• One eDP 4L
• One DPI 24-bit RGB parallel interface
• OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
• Safety features such as freeze frame detection and MISR data check

• 3D Graphics Processing Unit
• IMG BSX-64-4, up to 800 MHz
• 50 GFLOPS, 4 GTexels/s
• >500 MTexels/s, >8 GFLOPs
• Supports at least 2 composition layers
• Supports up to 2048x1080 @60fps
• Supports ARGB32, RGB565 and YUV formats
• 2D graphics capable
• OpenGL ES 3.1, Vulkan 1.2

• Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
• MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
• Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
• ECC verification/correction with CRC check + ECC on RAM
• Virtual Channel support (up to 16)
• Ability to write stream data directly to DDR via DMA

• Two Video Encoder/Decoder Modules
• Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
• Support for H.264 BaseLine/Main/High Profiles at Level 5.2
• Support for up to 4K UHD resolution (3840 × 2160) per module
• Each module supports 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

Memory subsystem:
• Up to 8MB of on-chip L3 RAM with ECC and coherency
• ECC error protection
• Shared coherent cache
• Supports internal DMA engine

• Up to Four External Memory Interface (EMIF) module with ECC
• Supports LPDDR4 memory types
• Supports speeds up to 4266 MT/s
• Up to 4x32-b bus with inline ECC up to 68 GB/s

• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected by ECC
• AEC-Q100 qualified on part number variants ending in Q1 Device security:
• Secure boot with secure run-time support
• Customer programmable root key, up to RSA-4K or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES High speed serial interfaces:
• Integrated Ethernet switch supporting up to 8 external ports
• Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
• All ports support 1Gb, 2.5Gb SGMII
• All ports can support QSGMII. A maximum of 2 QSGMII can be enabled and uses all 8 internal lanes. 1 QSGMII interfaces uses 4 internal lanes.

• Up to 4x2-L/2x4L PCI-Express (PCIe) Gen3 controllers
• Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation

• One USB 3.0 dual-role device (DRD) subsystem
• Enhanced SuperSpeed Gen1 Port
• Supports Type-C switching
• Independently configurable as USB host, USB peripheral, or USB DRD
Ethernet
• Two RGMII/RMII interfaces Automotive interfaces:
• Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support Audio interfaces:
• Five Multichannel Audio Serial Port (MCASP) modules Flash memory interfaces:
• Embedded MultiMediaCard Interface ( eMMC™ 5.1)
• One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
• Universal Flash Storage (UFS 2.1) interface with two lanes
• Two independent flash interfaces configured as
• One OSPI or HyperBus™ or QSPI flash interfaces, and
• One QSPI flash interface
System-on-Chip (SoC) architecture:
• 16-nm FinFET technology
• 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing TPS6594-Q1 Companion Power Management ICs (PMIC):
• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases