AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

AM68x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：5.11099 Mbytes 页数：253 Pages

TI

德州仪器

丝印：AM68A72ATGGHAALZ206；Package：FCBGA；AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

丝印：AM68A92ATGGHAALZ206；Package：FCBGA；AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

丝印：AM68A92A；Package：FCBGA；AM68x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：5.11099 Mbytes 页数：253 Pages

TI

德州仪器

AM68x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：5.11099 Mbytes 页数：253 Pages

TI

德州仪器

AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

适用于 1 至 8 个摄像头、机器视觉、智能交通、零售自动化的 8 TOPS 视觉 SoC

AM68 可扩展处理器系列采用不断发展的 Jacinto™ 7 架构，面向智能视觉摄像头和通用计算应用，基于 TI 在视觉处理器市场上十多年所积累的广泛先进市场知识而构建。AM68x 系列专为工厂自动化、楼宇自动化和其他市场中广泛的成本敏感型高性能计算应用而构建。\n\n AM68 以业界卓越的功耗/性能比为传统和深度学习算法提供高性能计算技术，并且系统集成度高，可为高级视觉摄像头应用实现可扩展性和更低的成本。关键内核包括用于常规计算的新款 Arm 和 GPU 处理器、具有标量和矢量内核的下一代 DSP、专用深度学习和传统算法加速器、集成的下一代成像子系统 (ISP)、视频编解码器和隔离式 M Processor cores: \n• 1MB shared L2 cache per dual-core Cortex-A72 cluster\n• Deep Learning Accelerator: \n• Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators\n• 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM\n• Dual-core Arm® Cortex®-;

TI

德州仪器