丝印：AM68A92A；Package：FCBGA；AM68x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：5.11099 Mbytes 页数：253 Pages

TI

德州仪器

丝印：AM68A92ATGGHAALZ206；Package：FCBGA；AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器

丝印：AM68A92A；Package：FCBGA；AM68x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：5.11099 Mbytes 页数：253 Pages

TI

德州仪器

丝印：AM68A92ATGGHAALZ206；Package：FCBGA；AM68Ax Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Secon

文件：4.74183 Mbytes 页数：251 Pages

TI

德州仪器