AM2634-Q1中文资料具有实时控制、ASIL-D 功能安全和信息安全且频率高达 400MHz 的四核 Arm® Cortex-R5F MCU数据手册TI规格书

特性 Features

Processor Cores:
• 16KB I-cache with 64-bit ECC per CPU core
• 64KB Tightly-Coupled Memory (TCM) with 32‑bit ECC per each R5F core
• 2MB of On-Chip RAM (OCSRAM)
• ECC error protection
• Dual-core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU_ICSSM) enabling industrial communication protocols or motor control interfaces:
• PROFINET
• IO-Link
• General Purpose Input/Output (GPIO)
• Real-time Control Subsystem (CONTROLSS)
• 5x 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC)
• 6 selectable inputs per ADC
• 1x 12-bit DAC with buffered output
• Extend the time resolution of the PWM compared to EPWM
• 10x enhanced Capture modules (ECAP)
• 2x Sigma-Delta Filter Modules (SDFM) each supporting up to 4 channels
• 1x EDMA to support data movement functions
• SPINLOCK module for synchronizing processes running on multiple cores
• Supports primary boot from the following interfaces:
• QSPI NOR Flash
• Time sync support with time sync and compare event interrupt routers
• Enables design of systems with functional safety requirements
• Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
• Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
• Functional Safety-Compliant targeted [Industrial]
• Documentation will be available to aid IEC 61508 functional safety system design
• Hardware integrity up to SIL-3 targeted
• IEC 61508 planned
• Functional Safety-Compliant targeted [Automotive]
• Documentation will be available to aid ISO 26262 functional safety system design
• Hardware integrity up to ASIL-D targeted
• ISO 26262 planned
• AEC-Q100 qualified for automotive applications
• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Device Take Over Protection
• Authenticated boot
• Debug security
• Provision to disable debug
• Device ID and Key Management
• Separate EFUSE controllers and FUSE ROMs
• Memory Protection Units (MPU)
• System MPU – present at various interfaces in the SoC (can be a firewall or MPU)
• Programmable (Privilege ID, Read/Write/Cachable, Start/End Address, Enable, Secure/Non Secure)
• Cryptographic acceleration
• AES - 128/192/256 bits key sizes
• DRBG with Pseudo and True Random number generator
• DMA support
• Integrated Ethernet switch supporting two external ports
• IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
• Packet Classifier based on ALE engine with 512 classifiers
• Packet size up to 2KB
• IP/UDP/TCP checksum offload in hardware
• 6x Universal Asynchronous Receiver-Transmitters (UART)
• 5x Local Interconnect Network (LIN) ports
• 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
• Fast Serial Interface (FSI) with 4x receiver cores and 4x transmitter cores
• 1x Multi-Media Card/Secure Digital (MMC/SD) 4-bit interface
• 16-bit parallel data bus
• Up to 4MB addressable memory space
• 45-nm technology
• 15mm x 15mm, 0.8-mm pitch, 324-pin NFBGA