AM2634-Q1数据手册TI中文资料规格书

特性 Features

Processor Cores:
• Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
• 16KB I-cache with 64-bit ECC per CPU core
• 16KB D-cache with 32-bit ECC per CPU core
• 64KB Tightly-Coupled Memory (TCM) with 32‑bit ECC per each R5F core
• Lock-step capability

Memory Subsystem:
• 2MB of On-Chip RAM (OCSRAM)
• 4 Banks x 512KB
• ECC error protection
• Supports internal DMA engine

Industrial Connectivity:
• Dual-core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU_ICSSM) enabling industrial communication protocols or motor control interfaces:
• EtherCAT
• PROFINET
• EtherNET/IP™
• IO-Link
• Encoder Feedback
• General Purpose Input/Output (GPIO)

Sensing & Actuation:
• Real-time Control Subsystem (CONTROLSS)
• 20x Analog Comparators with programmable DAC reference (CMPSS)
• 5x 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC)
• Up to 4 MSPS per ADC
• 6 selectable inputs per ADC
• Configurable as single-ended or differential inputs

• 1x 12-bit DAC with buffered output
• 32x enhanced High Resolution PWM modules (EHRPWM)
• Extend the time resolution of the PWM compared to EPWM
• Support single-ended or differential outputs

• 10x enhanced Capture modules (ECAP)
• 3x enhanced Quadrature Encoder Pulse modules (EQEP)
• 2x Sigma-Delta Filter Modules (SDFM) each supporting up to 4 channels
• Flexible signal multiplex crossbar (XBAR)
System on Chip (SoC) Services and Architecture:
• 1x EDMA to support data movement functions
• Interprocessor communication modules
• SPINLOCK module for synchronizing processes running on multiple cores
• MAILBOX functionality implemented through CTRLMMR registers

• Supports primary boot from the following interfaces:
• UART
• QSPI NOR Flash

• Time sync support with time sync and compare event interrupt routers
Functional Safety:
• Enables design of systems with functional safety requirements
• ECC or parity on calculation-critical memories
• Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
• Error Signal Module (ESM) with error pin
• Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks

• Functional Safety-Compliant targeted [Industrial]
• Developed for functional safety applications
• Documentation will be available to aid IEC 61508 functional safety system design
• Systematic capability up to SIL-3 targeted
• Hardware integrity up to SIL-3 targeted
• Safety-related certification
• IEC 61508 planned


• Functional Safety-Compliant targeted [Automotive]
• Developed for functional safety applications
• Documentation will be available to aid ISO 26262 functional safety system design
• Systematic capability up to ASIL-D targeted
• Hardware integrity up to ASIL-D targeted
• Safety-related certification
• ISO 26262 planned


• AEC-Q100 qualified for automotive applications
Security:
• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Secure boot support
• Device Take Over Protection
• Hardware-enforced root-of-trust
• Authenticated boot
• S/W Anti-rollback Protection

• Debug security
• Debug of HS device allowed only with proper authentication
• Provision to disable debug

• Device ID and Key Management
• Support for OTP Memory (FUSEROM) to store Root Keys & other security enabling fields
• Separate EFUSE controllers and FUSE ROMs
• Unique Device Public IDs

• Memory Protection Units (MPU)
• Arm® MPU present inside each Cortex®-R5F core

• System MPU – present at various interfaces in the SoC (can be a firewall or MPU)
• 8-16 Regions
• Programmable (Privilege ID, Read/Write/Cachable, Start/End Address, Enable, Secure/Non Secure)



• Cryptographic acceleration
• Supports cryptographic cores
• AES - 128/192/256 bits key sizes
• SHA2 - 256/384/512 bit support
• DRBG with Pseudo and True Random number generator
• PKA (public key accelerator) to assist in RSA/ECC processing

• DMA support

High-Speed Interfaces:
• Integrated Ethernet switch supporting two external ports
• RMII(10/100) or RGMII (10/100/1000)
• IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
• Clause 45 MDIO PHY management
• Packet Classifier based on ALE engine with 512 classifiers
• Priority based flow control
• Packet size up to 2KB
• Four CPU H/W interrupt Pacing
• IP/UDP/TCP checksum offload in hardware

Connectivity:
• 6x Universal Asynchronous Receiver-Transmitters (UART)
• 5x Serial Peripheral Interface (SPI) controllers
• 5x Local Interconnect Network (LIN) ports
• 4x Inter-Integrated Circuit (I2C) ports
• 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
• 1x Quad Serial Peripheral Interface (QSPI)
• Fast Serial Interface (FSI) with 4x receiver cores and 4x transmitter cores
• Up to 140 General-Purpose I/O (GPIO) pins
Media and Data Storage:
• 1x Multi-Media Card/Secure Digital (MMC/SD) 4-bit interface
• General-Purpose Memory Controller (GPMC)
• 16-bit parallel data bus
• 22-bit address bus
• Up to 4MB addressable memory space
• Integrated Error Location Module (ELM) support for error checking

Technology / Package:
• 45-nm technology
• 15mm x 15mm, 0.8-mm pitch, 324-pin NFBGA