AM2631-Q1中文资料具有实时控制和安全功能且频率高达 400MHz 的汽车类单核 Arm® Cortex®-R5F MCU数据手册TI规格书

描述 Description

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules.

The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.

TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.

特性 Features

Processor Cores:
• 16KB I-cache with 64-bit ECC per CPU core
• 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
• 2MB of On-Chip RAM (OCSRAM)
• ECC error protection
• 1x EDMA to support data movement functions
• UART (Primary/Backup)
• Interprocessor communication modules
• MAILBOX functionality implemented through CTRLMMR registers
• Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers
• 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
• 16-bit parallel data bus with 22-bit address bus
• Integrated Error Location Module (ELM) support for error checking
• 6x Universal Asynchronous RX-TX (UART)
• 5x Local Interconnect Network (LIN) ports
• 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
• 4x Fast Serial Interface Transmitters (FSITX)
• Up to 140 General-Purpose I/O (GPIO) pins
• Real-time Control Subsystem (CONTROLSS)
• 5x 12-bit Analog-to-Digital Converters (ADC)
• 6x Single-ended channels OR
• Highly Configurable ADC Digital Logic
• User-defined Sample and Hold (S+H)
• 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
• 1x 12-bit Digital-to-Analog Converter (DAC)
• Single or Dual PWM channels
• Extended HRPWM time resolution
• 10x Enhanced Capture (ECAP) modules
• 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
• Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
• Deterministic Hardware
• 20-channel enhanced input (eGPI) per PRU
• Embedded Peripherals and Memory
• 1x MDIO, 1x IEP,
• 2x 8KB Shared Data RAM
• ScratchPad (SPAD), MAC/CRC
• Digital encoder and sigma-delta control loops
• EtherCAT, Ethernet/IP™,
• Dedicated Interrupt Controller (INTC)
• Integrated Ethernet switch supporting two external ports
• IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
• 512x ALE engine-based Packet Classifiers
• Four CPU hardware interrupt pacing
• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Device Take Over Protection
• Authenticated boot
• Debug security
• Ability to disable device debug functionality
• Device ID and Key Management
• Store root keys & other security fields
• Separate EFUSE controllers and FUSE ROMs
• Memory Protection Units (MPU)
• System MPU - present at various interfaces in the SoC (MPU or Firewall)
• Enable/Privilege ID
• Read/Write/Cachable
• Cryptographic Acceleration
• AES - 128/192/256-bit key sizes
• DRBG with pseudo and true random number generator
• Enables design of systems with functional safety requirements
• ECC or parity on calculation-critical memories
• Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
• Functional Safety-Compliant targeted [Industrial]
• Documentation to be made available to aid IEC 61508 functional safety system design
• Hardware integrity up to SIL-3 targeted
• IEC 61508 planned
• Functional Safety-Compliant targeted [Automotive]
• Documentation to be made available to aid ISO 26262 functional safety system design
• Hardware integrity up to ASIL-D targeted
• ISO 26262 planned
• AEC-Q100 qualified for automotive applications
• ZCZ Package
• 15.0 mm x 15.0 mm
• 0.8 mm pitch