丝印：ADS52J65；Package：VQFN；ADS52J65 8-Channel, 16-Bit, 125-MSPS, 70-mW/Ch ADC With JESD204B Interface

1 Features 1• 16-Bit Resolution, Idle SNR: 80 dBFS • 70 mW/Ch at 125 MSPS, 4-CH per Lane • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane • Full-Scale Input: 2 VPP • Full-Scale SNR: 78 dBFS at fin = 10 MHz • Full-Scale SFDR: –85 dBc at fin = 10 MHz • Analog Input –3 dB Bandwidth = 250 MHz • Maximum

文件：856.61 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN(RGC)；ADS52J6x, 8/4-Channel, 16/14-Bit, 125MSPS, 70mW/Ch for 8-CH ADC With JESD204B Interface

1 Features • 16/14-Bit Resolution, 8/4-Channel ADC • Idle Signal-to-Noise Ratio (SNR): – 80dBFS for 16bit ADC – 79dBFS for 14bit ADC • Power dissipation at 125MSPS, 4CH per Lane: – 70mW/Ch for ADS52J65/66 (8CH ADC) – 82mW/Ch for ADS52J67/68 (4CH ADC) • Power dissipation at 62.5MSPS, 8CH pe

文件：1.1534 Mbytes 页数：13 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN；ADS52J65 8-Channel, 16-Bit, 125-MSPS, 70-mW/Ch ADC With JESD204B Interface

1 Features 1• 16-Bit Resolution, Idle SNR: 80 dBFS • 70 mW/Ch at 125 MSPS, 4-CH per Lane • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane • Full-Scale Input: 2 VPP • Full-Scale SNR: 78 dBFS at fin = 10 MHz • Full-Scale SFDR: –85 dBc at fin = 10 MHz • Analog Input –3 dB Bandwidth = 250 MHz • Maximum

文件：856.61 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN(RGC)；ADS52J6x, 8/4-Channel, 16/14-Bit, 125MSPS, 70mW/Ch for 8-CH ADC With JESD204B Interface

1 Features • 16/14-Bit Resolution, 8/4-Channel ADC • Idle Signal-to-Noise Ratio (SNR): – 80dBFS for 16bit ADC – 79dBFS for 14bit ADC • Power dissipation at 125MSPS, 4CH per Lane: – 70mW/Ch for ADS52J65/66 (8CH ADC) – 82mW/Ch for ADS52J67/68 (4CH ADC) • Power dissipation at 62.5MSPS, 8CH pe

文件：1.1534 Mbytes 页数：13 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN(RGC)；ADS52J6x, 8/4-Channel, 16/14-Bit, 125MSPS, 70mW/Ch for 8-CH ADC With JESD204B Interface

1 Features • 16/14-Bit Resolution, 8/4-Channel ADC • Idle Signal-to-Noise Ratio (SNR): – 80dBFS for 16bit ADC – 79dBFS for 14bit ADC • Power dissipation at 125MSPS, 4CH per Lane: – 70mW/Ch for ADS52J65/66 (8CH ADC) – 82mW/Ch for ADS52J67/68 (4CH ADC) • Power dissipation at 62.5MSPS, 8CH pe

文件：1.1534 Mbytes 页数：13 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN；ADS52J65 8-Channel, 16-Bit, 125-MSPS, 70-mW/Ch ADC With JESD204B Interface

1 Features 1• 16-Bit Resolution, Idle SNR: 80 dBFS • 70 mW/Ch at 125 MSPS, 4-CH per Lane • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane • Full-Scale Input: 2 VPP • Full-Scale SNR: 78 dBFS at fin = 10 MHz • Full-Scale SFDR: –85 dBc at fin = 10 MHz • Analog Input –3 dB Bandwidth = 250 MHz • Maximum

文件：856.61 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN；ADS52J65 8-Channel, 16-Bit, 125-MSPS, 70-mW/Ch ADC With JESD204B Interface

1 Features 1• 16-Bit Resolution, Idle SNR: 80 dBFS • 70 mW/Ch at 125 MSPS, 4-CH per Lane • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane • Full-Scale Input: 2 VPP • Full-Scale SNR: 78 dBFS at fin = 10 MHz • Full-Scale SFDR: –85 dBc at fin = 10 MHz • Analog Input –3 dB Bandwidth = 250 MHz • Maximum

文件：856.61 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN(RGC)；ADS52J6x, 8/4-Channel, 16/14-Bit, 125MSPS, 70mW/Ch for 8-CH ADC With JESD204B Interface

1 Features • 16/14-Bit Resolution, 8/4-Channel ADC • Idle Signal-to-Noise Ratio (SNR): – 80dBFS for 16bit ADC – 79dBFS for 14bit ADC • Power dissipation at 125MSPS, 4CH per Lane: – 70mW/Ch for ADS52J65/66 (8CH ADC) – 82mW/Ch for ADS52J67/68 (4CH ADC) • Power dissipation at 62.5MSPS, 8CH pe

文件：1.1534 Mbytes 页数：13 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN；8-Channel, 16-Bit, 125-MSPS, 70 mW/Ch ADC With JESD204B Interface

文件：755.76 Kbytes 页数：10 Pages

TI

德州仪器

丝印：ADS52J65；Package：VQFN；ADS52J65 8-Channel, 16-Bit, 125-MSPS, 70-mW/Ch ADC With JESD204B Interface

文件：1.33554 Mbytes 页数：12 Pages

TI

德州仪器