ADF4382A中文资料亚德诺数据手册PDF规格书

FEATURES

► Fundamental output frequency range: 11.5 GHz to 21 GHz

► Divide by 2 output frequency range: 5.75 GHz to 10.5 GHz

► Divide by 4 output frequency range: 2.875 GHz to 5.25 GHz

► Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth:

100 Hz to 100 MHz)

► Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)

► VCO fast calibration time < 1 μs

► VCO autocalibration time < 100 μs

► Phase noise floor: −156 dBc/Hz at 20 GHz

► PLL specifications

► −239 dBc/Hz: normalized in-band phase noise floor

► −287 dBc/Hz: normalized 1/f phase noise floor

► 625 MHz maximum phase/frequency detector input frequency

► 4.5 GHz reference input frequency

► Typical spurious fPFD: −90 dBc

► Reference to output delay specifications

► Propagation delay temperature coefficient: 0.06 ps/°C

► Adjustment step size: <1 ps

► Multichip output phase alignment

► 3.3 V and 5 V power supplies

► ADIsimPLL™ loop filter design tool support

► 7 mm × 7 mm, 48-terminal LGA

► −40°C to +105°C operating temperature

APPLICATIONS

► High performance data converter clocking

► Wireless infrastructure (MC-GSM, 5G, 6G)

► Test and measurement