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ADF4377BCCZ-RL7中文资料亚德诺数据手册PDF规格书

ADF4377BCCZ-RL7
厂商型号

ADF4377BCCZ-RL7

功能描述

Microwave Wideband Synthesizer with Integrated VCO

文件大小

4.88139 Mbytes

页面数量

79

生产厂商 Analog Devices
企业简称

AD亚德诺

中文名称

亚德诺半导体技术有限公司官网

原厂标识
AD
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-2 20:59:00

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ADF4377BCCZ-RL7规格书详情

GENERAL DESCRIPTION

The ADF4377 is a high performance, ultralow jitter, dual output

integer-N phased locked loop (PLL) with an integrated voltage controlled

oscillator (VCO) ideally suited for data converter and mixed

signal front end (MxFE) clock applications. The high performance

PLL has a figure of merit of −239 dBc/Hz, ultralow 1/f noise, and

a high phase frequency detector (PFD) frequency that can achieve

ultralow in-band noise and integrated jitter. The fundamental VCO

and output divider of the ADF4377 generate frequencies from 800

MHz to 12.8 GHz. The ADF4377 integrates all necessary power

supply bypass capacitors, saving board space on compact boards.

For multiple data converter and MxFE clock applications, the

ADF4377 simplifies clock alignment and calibration routines required

with other clock solutions by implementing the automatic

reference to output synchronization feature, the matched reference

to output delays across process, voltage, and temperature feature,

and the less than ±0.1 ps, jitter free reference to output delay

adjustment capability feature.

These features allow for predictable and precise multichip clock and

system reference (SYSREF) alignment. JESD204B and JESD204C

Subclass 1 solutions are supported by pairing the ADF4377 with

an integrated circuit (IC) that distributes pairs of reference and

SYSREF signals.

FEATURES

► Output frequency range: 800 MHz to 12.8 GHz

► Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz)

► Jitter = 27 fsRMS (ADC SNR method)

► Wideband noise floor: −160 dBc/Hz at 12 GHz

► PLL specifications

► −239 dBc/Hz: normalized in-band phase noise floor

► −147 dBc/Hz: normalized in-band 1/f noise

► Phase detector frequency up to 500 MHz

► Reference input frequency up to 1000 MHz

► Typical spurious fPFD: −95 dBc at fOUT = 12 GHz

► Reference input to output delay specifications

► Device-to-device standard deviation: 3 ps

► Temperature coefficient: 0.03 ps/°C

► Adjustment step size: < ±0.1 ps

► Multichip output phase alignment

► 3.3 V and 5 V power supplies

► 7 mm × 7 mm 48-lead LGA

APPLICATIONS

► High performance data converter and MxFE clocking

► Wireless infrastructure (MC-GSM, 5G)

► Test and measurement

供应商 型号 品牌 批号 封装 库存 备注 价格
ADI/亚德诺
22+
66900
原封装
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ADI/亚德诺
2511
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66900
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8659
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2450+
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6540
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17+
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6200
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ADI
21+
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12588
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ADI/亚德诺
25+
原厂封装
10280
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专营ADI
24+
QFN
9600
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ADI
18+
LFCSP
85600
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2447
TSSOP
100500
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询价