Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 页数：20 Pages

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整数N分频时钟转换器，适合有线通信应用

AD9550是一款基于锁相环(PLL)的时钟转换器，针对有线通信和基站应用的需求而设计。它采用整数N分频PLL来满足相关的频率转换要求。REF输入端支持单端输入参考信号。\n\n AD9550的引脚可编程，提供从15个可能的输入频率转换到51个可能的输出频率对（OUT1和OUT2）的标准输入/输出频率转换矩阵。\n\n 虽然AD9550严格按照CMOS工艺制造，但其输出与LVPECL、LVDS或单端CMOS逻辑电平兼容。\n\n AD9550的工作温度范围为−40°C至+85°C工业温度范围。 • 将预设标准输入频率转换为标准输出频率 \n• 输入频率范围：8 kHz至200 MHz \n• 输出频率最高可达810 MHz LVPECL和LVDS (200 MHz CMOS) \n• 预设引脚可编程频率转换比 \n• 片内VCO;

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Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 页数：20 Pages

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亚德诺

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 页数：20 Pages

AD

亚德诺

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 页数：20 Pages

AD

亚德诺

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 页数：20 Pages

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包装：盒 功能：时钟缓冲器/驱动器/接收器/转换器 类别：开发板，套件，编程器 评估和演示板及套件 描述：BOARD EVALUATION FOR AD9550

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Package：32-WFQFN 裸露焊盘，CSP；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 应用特定时钟/定时 描述：IC INTEGER-N TRANSLATOR 32-LFCSP

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Package：32-WFQFN 裸露焊盘，CSP；包装：卷带（TR）剪切带（CT）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 应用特定时钟/定时 描述：IC INTEGER-N TRANSLATOR 32-LFCSP

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