Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

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AD9525旨在满足长期演进(LTE)和多载波GSM基站设计的转换器时钟要求。

AD9525旨在满足长期演进(LTE)和多载波GSM基站设计的转换器时钟要求。\n\n AD9525提供低功耗、多路输出时钟分配功能，具有低抖动性能，并且片内集成锁相环（PLL），可以配合外部VCO或VCXO使用。VCO输入和八个LVPECL输出最高工作频率为3.6 GHz。所有输出共用一个分频器，分频范围为1到6。\n\n AD9525提供了一个专用输出，可用于提供一个用于重置或同步数据转换器的可编程信号。输出信号可以通过一个SPI写入操作激活。\n\n AD9525提供48引脚LFCSP封装，可以采用3.3 V单电源供电。外部VCXO或VCO的工作电压最高可达 • 集成超低噪声频率合成器;

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Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

亚德诺

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

亚德诺

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

亚德诺

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

亚德诺

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

亚德诺

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 页数：48 Pages

AD

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Low Jitter Clock Generator with Eight LVPECL Outputs

文件：852.11 Kbytes 页数：48 Pages

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包装：散装 功能：时钟发生器 类别：开发板，套件，编程器 评估和演示板及套件 描述：KIT EVAL FOR CRO29508

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