800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

文件：125.29 Kbytes 页数：2 Pages

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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

文件：967.31 Kbytes 页数：48 Pages

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1.2 GHz时钟分配IC、2路1.6 GHz输入、分频器、延迟调整、5路输出

AD9512提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。\n\n 3路独立的LVPECL时钟输出和2路LVDS时钟输出工作频率分别为1.2 GHz和800 MHz。可选的CMOS时钟输出工作频率为250 MHz。每路输出都有一个可编程分频器，可以旁路该分频器或者设置最高32的整数分频比。\n\n 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。1路输出还提供可编程延迟特性，具有最长10 ns的用户可选满量程延迟值。该精调延迟模块通过一个5位字进行编程 • 两路1.6 GHz差分时钟输入\n\n• 5个可编程分频器，1至32整数分频比\n\n• 用于输出到输出延迟粗调的相位选择\n\n• 3路独立的1.2 GHz LVPECL输出\n加性输出抖动：225 fs均方根值\n\n• 2路独立的800 MHz/250 MHz LVDS/CMOS输出\n加性输出抖动：275 fs均方根值\n1路输出提供延迟精调，5位延迟字\n\n• 4线式或3线式串行控制端口\n\n• 节省空间的48引脚LFCSP封装\n\n\nAD9512-EP支持防务和航空航天应用（AQEC标准）\n• 下载 AD9512-EP 数据手册 (pdf)\n\n• 军用温度范围\n;

ADI

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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

文件：967.31 Kbytes 页数：48 Pages

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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

文件：967.31 Kbytes 页数：48 Pages

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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs

GENERAL DESCRIPTION The AD9512-EP provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are fiv

文件：326.02 Kbytes 页数：20 Pages

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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

文件：967.31 Kbytes 页数：48 Pages

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亚德诺

1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs

GENERAL DESCRIPTION The AD9512-EP provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are fiv

文件：326.02 Kbytes 页数：20 Pages

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亚德诺

1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs

GENERAL DESCRIPTION The AD9512-EP provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are fiv

文件：326.02 Kbytes 页数：20 Pages

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Package：48-VFQFN 裸露焊盘，CSP；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 2:5 1.2GHZ 48LFCSP

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