65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：354.46 Kbytes 页数：43 Pages

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亚德诺

65 MSPS数字接收信号处理器

ADI公司的创新型分集接收机芯片组是一个紧凑的综合解决方案，提供两个中频至基带分集通道，片内集成了自动增益控制、接收信号强度指示器、高分辨率数字控制振荡器(NCO)和数字滤波。\n该芯片组内置ADI公司的双通道中频采样模数转换器AD6600和双通道抽取接收机芯片AD6620，配置适当的外部元件，就能够处理各种各样的空中接口标准，包括GSM、CDMA、IS136和PHS，以及用于寻呼系统和无线固定接入接收机的专有调制方案。该分集接收机基于ADI公司的新一代接收机架构，用数字滤波器取代了灵敏的模拟滤波器，从而显著降低了成本、缩小了尺寸。完整的参考设计所展示的最佳布局，不仅可降低噪声，还使跨通道耦合 高输入采样速率\n单通道实信号：67 MSPS\n分集通道实信号：33.5 MSPS\n单通道复信号：33.5 MSPS\nNCO频率转换\n最差杂散优于–100 dBc\n调谐分辨率优于0.02 Hz\n二阶级联积分器梳状FIR滤波器\n线性相位、固定系数\n可编程抽取率：2、3 . . . 16\n五阶级联积分器\n梳状FIR滤波器\n线性相位、固定系数\n可编程抽取率：\n1、2、3 . . . 32\n可编程抽取RAM\n系数FIR滤波器\n最高每秒1.34亿点\n256 20位可编程系数\n可编程抽取率：\n1、2、3 . . . 32;

ADI

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65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：354.46 Kbytes 页数：43 Pages

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：374.89 Kbytes 页数：44 Pages

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：374.89 Kbytes 页数：44 Pages

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：354.46 Kbytes 页数：43 Pages

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：354.46 Kbytes 页数：43 Pages

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：354.46 Kbytes 页数：43 Pages

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：374.89 Kbytes 页数：44 Pages

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

文件：374.89 Kbytes 页数：44 Pages

AD

亚德诺