9FGV0641数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power PCIe clock family. The device has integrated 100 ohm output terminations providing direction connection to 100 ohm transmission lines. The device also has 6 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

特性 Features

PCIe Gen1–4 compliant
LP-HCSL outputs with integrated terminations; save 24 resistors compared to standard PCIe devices
54 mW typical power consumption; reduced thermal concerns
Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable slew rate for each output; allows tuning for various line lengths
Programmable output amplitude; allows tuning for various application environments
DIF outputs blocked until PLL is locked; clean system start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
Configuration can be accomplished with strapping pins; SMBus interface not required for device control
3.3 V tolerant SMBus interface works with legacy controllers
Space saving 5x5 mm 40-pin VFQFPN; minimal board space
Selectable SMBus addresses; multiple devices can easily share an SMBus segment

应用 Application

• RZ/G2M 多显示器人机界面 SoM 解决方案
• 具有 AI 功能的可扩展人机界面 SMARC SoM
• 无线数字标牌
• 无线网络视频录像机
• 高性能 HMI 系统