9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer

Description The 9DBU0931 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. The device has 9 output enables for clock management, and 3 selectable SMBus addresses. Features/Benefits • LP-HCSL outputs; save 18 resistors compared to standard HCSL outputs • 47mW typical power consu

文件：407.3 Kbytes 页数：18 Pages

RENESAS

瑞萨

9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

Description The 9DBU0941 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 transmission lines. The device has 9 output enables for clock management, and 3 selectable SMBus addresses. Features/Benefits • Direct connect

文件：412.5 Kbytes 页数：18 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

Description The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Features/Benefits • LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced ther

文件：750.89 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

• LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced thermal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction • OE# pins; support DIF power management • HCSL compatible differential input; can

文件：721.05 Kbytes 页数：17 Pages

RENESAS

瑞萨

2-Output 1.8V PCIe Zero Delay/Fanout Clock Buffer with Zo = 100ohms

Description The 9DBV0241 is a member of Renesas' 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Features/Benefits • LP-HCSL outputs with Zo = 100; saves 8 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mod

文件：756.12 Kbytes 页数：17 Pages

RENESAS

瑞萨