1-to-12, Differential HCSL Fanout Buffer

General Description The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The 8V31012 is designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination

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1:4 LVDS Fanout Buffer with 2-Input Multiplexer for 1PPS Applications

General Description The 8V34S204 is a differential 1:4 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential i

文件：1.27034 Mbytes 页数：23 Pages

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1:8 LVDS Fanout Buffer with 2-Input Multiplexer for 1PPS Applications

General Description The 8V34S208 is a differential 1:8 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential i

文件：861.67 Kbytes 页数：22 Pages

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1-to-12, Differential HCSL Fanout Buffer

文件：455.32 Kbytes 页数：17 Pages

IDT

1-to-12, Differential HCSL Fanout Buffer

文件：455.32 Kbytes 页数：17 Pages

IDT

1-to-12, Differential HCSL Fanout Buffer

文件：455.32 Kbytes 页数：17 Pages

IDT

Four differential LVDS output pairs

文件：728 Kbytes 页数：22 Pages

IDT

Eight differential LVDS output pairs

文件：662.03 Kbytes 页数：21 Pages

IDT

1-to-12, Differential HCSL Fanout Buffer

The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The 8V31012 is designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resisto ·Twelve differential HCSL outputs\n·Translates any differential input signal (LVPECL, LVHSTL, LVDS, HCSL) to HCSL levels without external bias networks\n·Maximum output frequency: 250MHz\n·Output skew: 265ps (typical)\n·VOH: 850mV (maximum)\n·Full 3.3V supply voltage\n·Available in lead-free (RoHS 6;

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1:8 LVDS Fanout Buffer with 2-Input Multiplexer for 1PPS Applications

The 8V34S208 is a differential 1:8 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential input stages accept both rec • Designed for 1PPS, 2kHz, 8kHz and 10MHz GPS clock signaldistribution\n• High speed 1:8 LVDS fanout buffer\n• Eight differential LVDS output pairs\n• 2:1 input multiplexer\n• Two selectable differential inputs accept LVDS and LVPECLsignals\n• Accepts rectangular and sinusoidal input signals\n• Two ;

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