Features

• Two low skew, low additive jitter LVPECL output pairs

• Two selectable, differential clock input pairs

• Differential pairs can accept the following differential input

levels: LVDS, LVPECL, CML

• Maximum input clock frequency: 2GHz

• Output skew: 5ps (typical)

• Propagation delay: 225ps (maximum)

• Low additive phase jitter, RMS, fREF = 156.25MHz, VPP = 1V,

12kHz – 20MHz: 36fs (maximum)

• Full 3.3V and 2.5V supply voltage

• Maximum device current consumption (IEE): 56mA (maximum)

• Available in lead-free (RoHS 6), 16-Lead VFQFPN package

• -40°C to 85°C ambient operating temperature

• Supports case temperature ≤105°C operations

• Accepts single-ended LVCMOS levels. See Applications section

• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also

accept single-ended LVCMOS levels. See Applications section

Wiring the Differential Input Levels to Accept Single-ended Levels

(Figure 1A and Figure 1B)

8SLVP2102ANLGI属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的8SLVP2102ANLGI时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。