丝印：202AI；Package：VFQFPN；Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

Features • Two low skew, low additive jitter LVPECL output pairs • Two selectable, differential clock input pairs • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML • Maximum input clock frequency: 2GHz • Output skew: 5ps (typical) • Propagation delay

文件：1.34977 Mbytes 页数：24 Pages

RENESAS

瑞萨

丝印：202AI；Package：VFQFPN；Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

Features • Two low skew, low additive jitter LVPECL output pairs • Two selectable, differential clock input pairs • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML • Maximum input clock frequency: 2GHz • Output skew: 5ps (typical) • Propagation delay

文件：1.34977 Mbytes 页数：24 Pages

RENESAS

瑞萨

丝印：202AI；Package：VFQFPN；Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

Features • Two low skew, low additive jitter LVPECL output pairs • Two selectable, differential clock input pairs • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML • Maximum input clock frequency: 2GHz • Output skew: 5ps (typical) • Propagation delay

文件：1.34977 Mbytes 页数：24 Pages

RENESAS

瑞萨

丝印：202AI；Package：VFQFPN；Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

Features • Two low skew, low additive jitter LVPECL output pairs • Two selectable, differential clock input pairs • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML • Maximum input clock frequency: 2GHz • Output skew: 5ps (typical) • Propagation delay

文件：1.34977 Mbytes 页数：24 Pages

RENESAS

瑞萨

丝印：202AI；Package：VFQFPN；2.5V LVPECL Output Fanout Buffer

文件：628.97 Kbytes 页数：23 Pages

IDT

丝印：202AI；Package：VFQFPN；2.5V LVPECL Output Fanout Buffer

文件：628.97 Kbytes 页数：23 Pages

IDT