8P391208中文资料Low Additive Jitter 2:8 Buffer with Universal Differential Outputs数据手册Renesas规格书

描述 Description

The 8P391208 is intended to take 1 or 2 reference clocks, select between them using a pin selection, and generate up to 8 outputs that are the same as the reference frequency. The 8P391208 supports two output banks, each with its own power supply. All outputs in one bank would generate the same output frequency, and each bank can be individually controlled for output type or output enable. The device can operate over the -40 to +85°C temperature range.

特性 Features

• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (1GHz in 3.3V HCSL mode)
• Two differential inputs support LVPECL, LVDS, LVHSTL, HCSL or LVCMOS reference clocks
• Generates 8 differential or 16 LVCMOS outputs
• Outputs arranged in two banks of four outputs each
• Select pins control which input drives which of two output banks
• Controlled by 3-level input pins that are 3.3V-tolerant for all core voltages
• Output type may be selected from LVPECL, LVDS, HCSL or CML
• Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V
• CML outputs support two different voltage swings
• Individual output enables and output type selection supported
• Output noise floor of –153dBc/Hz @ 156.25MHz
• Core voltage supply of 3.3V, 2.5V or 1.8V
• -40 to +85°C ambient operating temperature
• Lead-free (RoHS 6) QFN-32 (5mm x 5mm) packaging

应用 Application

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