8P34S1212数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The 8P34S1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1212 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the differential device input. The device is optimized for low power consumption and low additive phase noise.

特性 Features

• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pair
• Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML
• Maximum input clock frequency: 1.5GHz
• Output skew: 10ps (typical)
• Propagation delay: 400ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, 10kHz–20MHz: 34fs (typical)
• Device current consumption (IDD):
• 185mA typical: 1.8V
• 200mA typical: 2.5V

应用 Application

• AI Industrial Robotics and Robotic Communication Solution
• 手持式超声扫描仪