8P34S2102数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The 8P34S2102 is a high-performance, low-power, differential dual 1:2 LVDS output, 1.8V/2.5V fanout buffer. The device supports fail-safe operation and is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available. Each channel has two low-skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2102 ideal for those clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V or a 2.5V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs.

特性 Features

Dual 1:2 low skew, low additive jitter LVDS fanout buffers
Matched AC characteristics across both channels
High isolation between channels
Low power consumption
Both differential CLKA, nCLKA and CLKB, nCLKB inputs accept LVDS, LVPECL and single-ended LVCMOS levels
Maximum input clock frequency: 2.0GHz
Output amplitudes: 350mV, 500mV (selectable)
Output bank skew: 5ps typical
Output skew: 30ps typical
Low additive phase jitter, RMS: 40fs typical (fREF = 156.25MHz, 12kHz to 20MHz)
Full 1.8V / 2.5V supply voltage mode
Lead-free (RoHS 6), 16-lead VFQFN packaging
-40°C to 85°C (Tc ≤ 105°C) operating temperature range

应用 Application

• AI Industrial Robotics and Robotic Communication Solution
• 手持式超声扫描仪