1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair • Differential CLK, nCLK input pair • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output

文件：620.39 Kbytes 页数：21 Pages

RENESAS

瑞萨

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：423.95 Kbytes 页数：20 Pages

IDT

1:1 Differential-to-LVDS Zero Delay Clock Generator

The 8745BI-21 is a highly versatile 1:1 LVDS Clock Generator. The 8745BI-21 has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each pro One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair\nDifferential CLK, nCLK input pair\nCLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\nOutput frequency range: 31.25M;

Renesas

瑞萨

Output frequency range

文件：898.32 Kbytes 页数：21 Pages

IDT