Output frequency range

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IDT

Output frequency range

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瑞萨

1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair • Differential CLK, nCLK input pair • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output

文件：620.39 Kbytes 页数：21 Pages

RENESAS

瑞萨

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：423.95 Kbytes 页数：20 Pages

IDT