2.5V Differential Clock Divider/Buffer

General Description The 874328I-01 is a high-performance differential ÷1 and ÷4 clock divider and fanout buffer. The device is designed for the frequency-division and signal fanout of high-frequency, low phase-noise clock signals. The differential input signal is frequency divided by ÷1 and ÷

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2.5V Differential Clock Divider/Buffer

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2.5V Differential Clock Divider/Buffer

The 874328I-01 is a high-performance differential ÷1 and ÷4 clock divider and fanout buffer. The device is designed for the frequency-division and signal fanout of high-frequency, low phase-noise clock signals. The differential input signal is frequency divided by ÷1 and ÷4. Three LVPECL and three L • One differential input LVPECL reference clock\n• Integrated input termination resistors\n• One bank of three LVPECL outputs (÷4 frequency-divided)\n• Two banks of three LVDS outputs (÷4 frequency-divided)\n• Total of twenty differential clock outputs\n• Maximum output frequency: 650MHz (÷1 outputs;

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上传：深圳市阅创想科技有限公司

Molex

莫仕

上传：深圳市阅创想科技有限公司