丝印：ICS8745BM-21LF；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair • Differential CLK, nCLK input pair • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output

文件：519.19 Kbytes 页数：20 Pages

RENESAS

瑞萨

丝印：ICS8745BM-21LF；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair • Differential CLK, nCLK input pair • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output

文件：519.19 Kbytes 页数：20 Pages

RENESAS

瑞萨

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK GEN 1:1 DIFF-LVDS 20-SOIC

Renesas Electronics America Inc

REALTEK
QFN-40

REALTEK

瑞昱

上传：深圳市禾兴威科技有限公司

Connector
MOLEX/莫仕

Connector

上传：深圳市长旗科技有限公司