丝印：8737；Package：FC-16；High efficiency, low noise, super low distortion, constant pitch volume, seventh generation K music.

文件：1.76375 Mbytes 页数：28 Pages

AWINIC

艾为电子

丝印：ICS8737AG11L；Package：TSSOP；Low Skew Differential-to-3.3V LVPECL Clock Generator

GENERAL DESCRIPTION The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input level

文件：228.15 Kbytes 页数：17 Pages

IDT

丝印：ICS8737AG11L；Package：TSSOP；Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports th

文件：425.98 Kbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8737AG11L；Package：TSSOP；Low Skew Differential-to-3.3V LVPECL Clock Generator

GENERAL DESCRIPTION The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input level

文件：228.15 Kbytes 页数：17 Pages

IDT

丝印：ICS8737AG11L；Package：TSSOP；Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports th

文件：425.98 Kbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8737AI11L；Package：TSSOP；Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

文件：550.08 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS8737AI11L；Package：TSSOP；Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

文件：550.08 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS8737AI11L；Package：TSSOP；Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes 页数：15 Pages

IDT

丝印：ICS8737AI11L；Package：TSSOP；Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes 页数：15 Pages

IDT

Audio Cable, #22-1pr, TC, O/A Braid, CM

Product Description 22 AWG stranded (7x30) tinned copper conductors, PVC insulation, twisted pair, tinned copper spiral wrapped shield (85 coverage), PVC jacket.

文件：161.99 Kbytes 页数：2 Pages

BELDEN

百通