丝印：ICS87008AGI；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

文件：292.03 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87008AGI；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 页数：16 Pages

IDT

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

文件：292.03 Kbytes 页数：16 Pages

RENESAS

瑞萨

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 页数：16 Pages

IDT

7.0A, 20V, 0.023 Ohm, Dual N-Channel, 2.5V Specified Power MOSFET

Features • Ultra Low On-Resistance - rDS(ON) = 0.023Ω, VGS = 4.5V - rDS(ON) = 0.024Ω, VGS = 4.0V - rDS(ON) = 0.029Ω, VGS = 2.5V • 2.5 Volt Gate Drive Capability • Gate to Source Protection Diode • Simulation Models - Temperature Compensated PSPICE™ and SABER Electrical Mode

文件：203.38 Kbytes 页数：13 Pages

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