丝印：ICS87008AGILF；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

文件：292.03 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87008AGILF；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 页数：16 Pages

IDT

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GENERATOR 1:8 24-TSSOP

Renesas Electronics America Inc

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 页数：16 Pages

IDT

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

文件：292.03 Kbytes 页数：16 Pages

RENESAS

瑞萨

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

文件：292.03 Kbytes 页数：16 Pages

RENESAS

瑞萨