2:2 Differential-to-LVPECL/LVDS Clock Multiplexer

The 859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagati • High speed 2:1 differential multiplexer with a 1:2 fanout buffer\n• Two differential LVPECL or LVDS output pairs\n• Two selectable differential PCLKx, nPCLKx input pairs\n• PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n• Maximum output frequency: ;

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Propagation delay

文件：668.02 Kbytes 页数：23 Pages

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2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

文件：1.12947 Mbytes 页数：24 Pages

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2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

文件：1.12947 Mbytes 页数：24 Pages

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2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

文件：1.12947 Mbytes 页数：24 Pages

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