859S0212I中文资料2:2 Differential-to-LVPECL/LVDS Clock Multiplexer数据手册Renesas规格书

描述 Description

The 859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pin has an internal pulldown resistor.

特性 Features

• High speed 2:1 differential multiplexer with a 1:2 fanout buffer
• Two differential LVPECL or LVDS output pairs
• Two selectable differential PCLKx, nPCLKx input pairs
• PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
• Part-to-part skew: 25ps (typical)
• Propagation delay: 555ps (typical)
• Additive phase jitter, RMS: 0.16ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package