丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

文件：1.42469 Mbytes 页数：23 Pages

RENESAS

瑞萨

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes 页数：23 Pages

IDT

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:2 3GHZ 16TSSOP

Renesas Electronics America Inc

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

文件：427.98 Kbytes 页数：19 Pages

IDT

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

文件：427.98 Kbytes 页数：19 Pages

IDT

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

文件：427.98 Kbytes 页数：19 Pages

IDT