丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

文件：1.42469 Mbytes 页数：23 Pages

RENESAS

瑞萨

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

文件：1.42469 Mbytes 页数：23 Pages

RENESAS

瑞萨

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes 页数：23 Pages

IDT

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes 页数：23 Pages

IDT