丝印：8532；Package：MSOP-8；OPERATION INSTRUCTION

文件：5.36007 Mbytes 页数：33 Pages

COREBAI

芯佰微

丝印：85322AML；Package：SOIC；Dual LVCMOS / LVTTL-to-Differential 2.5V / 3.3V LVPECL Translator

FEATURES • Two differential 2.5V/3.3V LVPECL outputs • Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 267MHz • Part-to-part skew: 250ps (maximum) • 3.3V operating supply voltage (operating

文件：323.84 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：85320AIL；Package：SOIC；LVCMOS/LVTTL-to-Differential 3.3V, 2.5V LVPECL Translator

FEATURES • One differential 2.5V/3.3V LVPECL output • LVCMOS/LVTTL CLK input • CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 267MHz • Part-to-part skew: 275ps (maximum) • Additive phase jitter, RMS: 0.05ps (typical) • 3.3V operating supply voltage (ope

文件：376.42 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：85320AIL；Package：SOIC；LVCMOS/LVTTL-to-Differential 3.3V, 2.5V LVPECL Translator

FEATURES • One differential 2.5V/3.3V LVPECL output • LVCMOS/LVTTL CLK input • CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 267MHz • Part-to-part skew: 275ps (maximum) • Additive phase jitter, RMS: 0.05ps (typical) • 3.3V operating supply voltage (ope

文件：376.42 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：85322AML；Package：SOIC；Dual LVCMOS / LVTTL-to-Different ial 2.5V / 3.3V LVPECL Translator

文件：160.49 Kbytes 页数：13 Pages

IDT

丝印：85322AML；Package：SOIC；Dual LVCMOS / LVTTL-to-Different ial 2.5V / 3.3V LVPECL Translator

文件：160.49 Kbytes 页数：13 Pages

IDT

丝印：85320AIL；Package：SOIC；LVCMOS/LVTTL-to-Differential 3.3V, 2.5V LVPECL Translator

文件：215.97 Kbytes 页数：16 Pages

IDT

丝印：85320AIL；Package：SOIC；LVCMOS/LVTTL-to-Differential 3.3V, 2.5V LVPECL Translator

文件：215.97 Kbytes 页数：16 Pages

IDT

丝印：85322AML；Package：SOIC；Dual LVCMOS / LVTTL-to-Differential 2.5V / 3.3V LVPECL Translator

FEATURES • Two differential 2.5V/3.3V LVPECL outputs • Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 267MHz • Part-to-part skew: 250ps (maximum) • 3.3V operating supply voltage (operating

文件：323.84 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：85322AML；Package：SOIC；Dual LVCMOS / LVTTL-to-Different ial 2.5V / 3.3V LVPECL Translator

文件：160.49 Kbytes 页数：13 Pages

IDT