700MHZ, FemtoClock® VCXO Based Sonet/SDH Jitter Attenuators

General Description The ICS843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage us

文件：550.11 Kbytes 页数：25 Pages

RENESAS

瑞萨

700MHZ, FemtoClock VCXO Based Sonet/SDH Jitter Attenuators

文件：341.32 Kbytes 页数：24 Pages

IDT

700MHz,FemtoClock® VCXO Based SONET/SDH Jitter Attenuator

The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized t ·Two Differential LVPECL outputs\n·Selectable CLKx, nCLKx differential input pairs\n·CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels\n·Maximum output frequency: 700MHz\n·FemtoClock VCO frequency range: 560M;

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瑞萨

700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

文件：277.72 Kbytes 页数：21 Pages

ICST

700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

文件：3.11985 Mbytes 页数：23 Pages

IDT